This invention relates generally to a data selection device, and more particularly to an image display controlling apparatus in which a data selection device is used for selecting one of a plurality of superimposed images commonly referred to as "sprites" on a screen of a raster scanning device.
Video display controlling apparatus capable of producing sprites must be able to move the sprites to any desired position on the screen. Each sprite is assigned a priority value. When two or more sprites have coordinates which overlap each other, only the sprite having the highest priority value will be displayed on the screen.
A conventional data selection device 50 for determining the priority order of a plurality of sprites is shown in FIG. 1. Device 50 can store sixteen different sprites, each having a width of 16 dots (i.e. pixels) along a horizontal scanning line of a screen of a cathode ray tube. Each dot is described by a 4 bit word of data. Each word of data can represent one of sixteen different types of characteristics concerning the dot. For example, each 4 bit word can represent one of sixteen different colors.
Device 50 includes sixteen different circuit blocks SP1-SP16 each of which includes a pattern shift circuit 11. Each pattern shift circuit 11 has four shift registers 15 each of which has a length of 16 bits. Each pattern shift circuit 11 also includes a latch circuit 16 for storing an X coordinate representing the position along the horizontal scanning line of the screen at which the 4 bit word of sprite data is to be displayed. A comparator 17 and a clock control circuit 18 are also included in each pattern shift circuit 11.
The sprite data to be displayed is stored within four shift registers 15 of each pattern shift circuit 11. Storage of the sprite data takes place during the horizontal blanking period of a cathode ray tube (CRT) just prior to the horizontal scanning line on which the sprite data is to be displayed. Parallel transmission of sprite data to shift registers 15 is provided through pattern input signal lines 100. Each shift register 15 stores the sprite data based on read-in clock signal CK which is supplied to shift registers 15 along read-in clock signal lines 102. Sprite data is stored first in circuit SP1 and then sequentially in circuits SP2-SP16.
As the data for each pattern shift circuit 11 is stored within its corresponding shift registers 15, the corresponding display coordinate (i.e. X-coordinate) is stored in a corresponding latch circuit 16 through an input line 101. A horizontal dot counter 19, which maintains a count corresponding to the point along the horizontal scanning line at which the beam from the CRT is located, is connected to each comparator 17 of each pattern shift circuit 11. Each comparator 17 compares the count value supplied by horizontal dot counter 19 to the value stored in an associated latch circuit 16. For example, when the values supplied from horizontal dot counter 19 and latch 16 of circuit SP1 are the same, comparator 17 of circuit SP1 produces a detection signal 104. Clock control circuit 18 of circuit SP1 upon receiving detecting signal 104 outputs a clock control signal 105 to each of the four shift registers 15 of circuit SP1. Sprite data stored within these shift registers 15 is sequentially outputted along four output lines 103 in synchronism with the clock control signal 105.
Connected to output lines 103 of circuit SP1 are four OR gates 14a, 14b, 14c and 14d of an OR circuit 14. Each of the OR gates 14a, 14b, 14c and 14d has sixteen inputs. Output lines 103 of circuit SP1 are also connected to four input terminals of a NOR gate 12a. NOR gate 12a produces a signal "a".
Each circuit block SP2-SP16 has an AND circuit 13a-13o, respectively. Each AND circuit 13a-13o has four AND gates. Output lines 103 of each circuit block SP2-SP16 are connected to first input terminals of the four gates of the associated AND circuit 13a-13o. The second input terminal of the four gates of AND circuits 13a-13o is connected to the output of NOR gate 12a. The outputs from each of the four gates of AND circuit 13a-13o are connected to one of the four gates 14a, 14b, 14c and 14d of OR circuit 14, respectively.
Each circuit block SP2-SP15 also includes a NOR gate 12b, 12c connected at its input to the output lines 103. As shown in FIG. 1, NOR gate 12b produces a signal "b" and NOR gate 12c produces a signal "c". In each circuit block for SP2-SP15 the output of each NOR gate is connected to an input of each gate within each AND circuit 13 of each higher numbered circuit block. For example, the output of NOR gate 12b of circuit block SP2 is connected as an input to AND gates 13b-13o. The output of NOR gate 12c of circuit block SP3 is connected as an input to AND gates 13c-13o.
Sprite data stored in each pattern shift circuit 11 is assigned a different priority value with the highest priority given to sprite data stored in circuit block SP1 and the lowest priority given to the sprite data stored in SP16 (i.e. the lower the number of the SP circuit, the higher its priority).
A four bit word of data having a value of (0,0,0,0) is considered non-selectable sprite data. For example, a word having a value of (0,0,0,0) describes the color of a dot considered transparent and would not be selected by device 50 (i.e. no selectable data exists). If selectable data does exist then at least one of the four bits of the word appearing on output lines 103 has a high logic level (i.e. a logic level of 1) .
When selectable data exists on output lines 103 of circuit block 103, signal "a" of NOR gate 12a has a logic level of 0. Since signal "a" is provided as an input to each gate of AND circuits 13a-13o, AND circuits 13a-13o output logic levels of 0. Therefore, the output from OR circuit 14 represents the pattern shift data stored within pattern shift circuit 11 of circuit block SP1.
When the outputs from shift registers 15 of circuit block SP1 (i.e. output lines 103) have a value of (0,0,0,0) a nonselectable data group exists. Signal "a" of NOR gate 12a changes to a logic level of 1. If selectable data exists on output lines 103 of circuit block SP2 signal "b" of NOR gate 12b assumes a logic level of 0. Since signal "b" is fed as an input to each of the gates of AND circuits 13b-13o, AND circuits 13b-13o assume a logic level of 0. Consequently, the outputs from OR circuit 14 will represent the pattern shift data stored within pattern shift circuit 11 of circuit block SP2.
Each of the remaining circuit blocks SP3-SP15 has a NOR gate (e.g. NOR gate 12c) which operate in a similar manner as NOR gates 12a and 12b to disable AND circuits 13c-13o, respectively. In other words, data selection device 50 provides a scheme which permits only data stored in the highest prioritized pattern shift circuit 11 to be supplied as the display pattern through OR circuit 14. Selectable data existing in circuit block SP1 has the highest priority and will be chosen over any other selectable data existing in any other circuit block. Selectable data existing in circuit block SP16 has the lowest priority and never will be chosen over any other selectable data existing in any other circuit block.
Data selection device 50 has several drawbacks. More particularly, NOR gate 12a is connected to more AND gates than is NOR gate 12b which is connected to more AND gates than is NOR gate 12c. In other words, each of the NOR gates of device 50 is connected to a different number of AND gates resulting in a different load across each output of each NOR gate. Signals "a", "b", "c"...produced from each of these NOR gates has a different delay time due to the different output loads. For example, the delay time of signal "a" is longer than the delay time of signal "b" which is longer than the delay time of signal "c".
The number of inputs for each of the AND gates varies depending on the SP circuit block and increases in number as the number of the SP circuit block increases. Generally, the larger the number of inputs for an AND gate the longer the delay time in providing an output signal therefrom. Accordingly, when the sprite data for SP16 is chosen, an unacceptably large access time is required. For high speed access applications, such delay times are undesirable.
The size of an integrated circuit should be as small as possible and is based on the number of logic gates which are required and the size of each logic gate required. The greater the number of inputs for any particular logic gate, the greater the size of the integrated circuit. Device 50 requires an integrated circuit having an undesirably large size.
Since each AND circuit 13a-13o of circuit blocks SP2-SP16 has a different number of inputs, standardization of the gates is not possible. Manufacture of AND circuits 13a-13o is also a problem since each AND circuit 13a-13o has a different size due to the different number of inputs required for each AND 13a-13o. The area occupied by each AND circuit 13a-13o is different complicating their layout on a semiconductor chip. The area occupied by wires associated with each AND gate 13a-13o also varies. For the foregoing reasons, device 50 requires too much space on a semiconductor chip.
Accordingly, it is desirable to provide a data selection device for selecting among data which has been prioritized having high speed access which is suitable for use with a semiconductor integrated circuit. The overall size of the data selection device should be reduced compared to conventional data selection devices. The logic gates should be standardized to optimize both the size of the device and reduce manufacturing costs of the device.